I'm a digital designer for mixed-signal projects. My field of expertises covers modeling, validation, HDL coding (both VHDL and Verilog), synthesis, static timing analysis, place & route and mixed-signals simulation. I work almost exclusively with analog designers to cover and validate all digital -analog interfaces.
I'm increasingly acting as a co-project leader in an industry domain where the quality requirements impose less than one failure per million of units produced.
I have the chance to do a job which turn to be also my passion. My interest for microelectronic goes far beyond my professional activity. I have a particular interest for advanced microprocessor design.
9 contacts
Ludovic Rota
Digital Project Leader
Bruxelles - Belgium
| English | French |
Schools attended |
Since 2008: ON Semiconductor |
Digital Project Leader
| |
· Acting as a Principal Digital Designer (Front-End & Back-End) & Co-project Leader (project management). · I manage different design teams and consultants in different countries (assign tasks, supervise progression, establish project plan and milestones, validate results). · I make digital specification proposals, write digital micro-architectures and all the test verification plans. | |
Sector: Electronics and microelectronics |
2004 - 2008 : AMI Semiconductor |
Mixed Signal Design Engineer
| |
· As a Digital Designer, my primary responsibility is to design specific digital blocks, both in VHDL or Verilog, to write corresponding testbenches for blocks verification, to implement logic for DFT, to develop Top Level verification (and System Level verification if possible), to synthesize the RTL code, to perform Static Timing Analysis, incremental synthesis and back-annotated verification, to perform Place & Route, to perform Formal Verification and Signoff, and to generate ATPG / IDDQ vectors for ATE. | |
Sector: Electronics and microelectronics |
1999 - 2004 : Integration Associates |
Mixed Signal Design Engineer
| |
· I had the responsibility to verify Third party digital blocks as a Verification Engineer (IP pre-transfer verification). · I was the Xilinx engineer for one of my former employer in the digital team, responsible for converting existing HDL code into synthesizable HDL code for Xilinx FPGA, to do the synthesis and the Place & Route. · I had also to write CAD tools for one of my former employer. | |
Sector: Electronics and microelectronics |