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Jean-Philippe Ulpiano

Munich - Germany

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Schools attended

ENSEEIHT (Engineering school)

Since 2004: Infineon (former LSI)

C++ SW Developper
• C++ development of OptiCM4, a GUI interface based on wxWidgets to drive a Perl written integrated Clearcase environment.
• Development of a multithreaded C++ / Perl interface performing direct accesses to the engine.
• wxWidgets GUI based interface driving the Clearcase environment through the C++ Perl interface.
• XMLRPC client/server interface allowing communication with other internal tools.
• mySQL client integration and requests definition to observe test results.
• ODBC integration for MSSQL.
• GUI functionalities based on many intuitive Wizards.
• Setup of meetings to request feed-back from future users during the development phase

• Technical leader for a GUI environment regression system development.
• Several investigation tools development written in Python for VOB corruptions
• Trainings: Network, CC Adminstration.
Sector: Telecom - Internet Products and Services

2002 - 2004 : Texas Instruments

Java / Python development engineer
Development of several tools for a regression system environment.
Automatisation of the overall process.
• C low level and ARM11 assembler development on OMAP1710, OMAP2420, Dolomites, OMAP2430, OMAP2140 projects.
• JAVA development of a profiler tool dedicated to embedded code optimization.
• Scripting development under UNIX / Solaris dedicated to validation automation.
• Python development of a coverage tool Purify like.
• Set up of a co simulation environment (Seamless) for Perseus 2 project.
• Attended trainings: JAVA/UML, UNIX administration.
Sector: Electronics and microelectronics

2000 - 2002 : Cadence

C++ development engineer
• Dynamic translator development on a hierarchical database for the Integration Ensemble project. This generates a GDSII file from Verilog (GDSII is normally dedicated to the foundry).
• Study of the databases intrinsic differences (busses and instances).
• Development of a C++ class managing a module replacement (VHDL/Verilog) by any other one integrating connectivities (front-end) and physicals (back-end) constraints.
• Development of a verilog writer generating a verilog file from any database content. Intensive use of multi site Clearcase.
• Csh shells scripts and verilog modules development for validation purposes.

• Attended C++ advanced formation course.
Sector: Software publishers

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