Cyrille THOMAS

Sector: Computer Equipment & Peripherals

Taking part in architectural choices for the next Bull ASIC in 90nm technology. The chip manages memory coherency in servers based on future Intel processor.

Responsible for logical design of the IC Physical Layer, in close collaboration with Avago Technology foundry (formerly Agilent) for integration of specified-by-Intel IPs (Common System Interface) and very high speed SerDes (8Gb/s).

Sector: Computer Equipment & Peripherals

Co-responsible for logical design and synthesis of an ASIC part in 180nm technology (FAME Scalability Switch, FSS).

The block links two FSS, which are 60 million transistors integrated circuits, essential chips of a 32 Intel Itanium2 processors server.

Co-responsible for chip timing constraints definition and application with IBM Static Timing Analysis tools.

Sector: Computer Equipment & Peripherals

First, development in Verilog of exciting/replying blocks for validation in global verification environment.

Then, design of a block on Xilinx FPGA target.

Sector: Computer Equipment & Peripherals

Integration and Prototyping team member, working on the design of a Firewire --> Ethernet protocols converter. Validation of VHDL units with System On Chip development platform (ARM-FPGA).

Sector: Electronics and microelectronics